|University of Florida|
|Computer and Information Science and
||301 CSE, P.O. Box 116120
Department of CISE
University of Florida
Gainesville, FL 32611
Dr. Peir received the Ph.D. degree in computer science from University
of Illinois in 1986. He joined IBM T. J. Watson Research Center and
served as a Research Staff Member during 1986-1992. At IBM, he
participated in the design and development of high-performance
mainframe computers. He
received an IBM Invention Achievement Award and filed several patents
in cache memories. During 1992-94, Dr. Peir joined the Computer and
Communication Lab in Taiwan as a Deputy Director of the Computer
System Division, where he was in charge of the development of an Intel
Pentium-based, symmetric multiprocessor system. He is currently an
Associate Processor at Computer and Information Science and
Engineering Department, University of Florida. Dr. Peir spent a
sabbatical year and several summers as a visiting professor at Intel’s
Microprocessor Research Lab in Portland, Oregon and at IBM’s Almaden
Research Center in San Jose, California.
extensive industrial background, Dr. Peir's major research and
teaching focus is on the high-performance computer system
architectures, microarchitectures and their memory hierarchy designs.
He also engages in researches of high-performance
chip-multiprocessors, graphics processors and network router
architectures. He has published over 90 papers in international
journals and conferences, and received two best paper awards. Dr. Peir
received an NSF Career Award and an IBM Research Partnership Award. He
also received an outstanding Alumni Award from the College of
Engineering, University of Wisconsin-Milwaukee. Dr. Peir served on the
Editorial Board of IEEE Transactions on Parallel and Distributed
Systems. He also served as a subject area editor for the
Journal of Parallel and Distributed Computing.
||GPU Architecture and Programming
|| Introduction to Computer Organiztion
||Computer Architecture Principles
- Memory Hierarchy Studies on Many-Core CMPs with Large On-Die
, Sponsor: Intel Corp.
- NeTS:Small:Making Online Network Functions Fast and Compact,
CRI:CRD Archer - Seeding a Community-based
Computing Infrastructure for Computer Architecture Research and
Education” Sponsor: NSF.
- Studies of
Memory Performance of Multithreaded Multimedia Workloads,
Sponsor: Microcomputer Research Lab, Intel Corp.
Multiprocessor Caching Techniques Based on Cache Interference
and Working Set Change, Sponsor: NSF-CISE/EIA.
Based DSM Architecture with Integrated on-Die Memory,
Sponsor: Microcomputer Research Lab, Intel Corp.
and Reforming Tag and Data Arrays for High-Performance Memory
Hierarchy Systems, Sponsor: NSF/CAREER Program.
- A Framework
for Matching Applications with Parallel Machines, Sponsor:
US Army Engineering Waterways Experiment Station.
- Undergraduate Laboratory Development for Computer Architecture and
Real-Timed Embedded Systems, Sponser: NSF Instrument and
Studies of Symmetric Multiprocessor Systems, Sponsor: IBM
Research Partnership Program.
“Small Cache Lookaside Table for Fast
DRAM Cache Access”,
X. Tao, Q. Zeng, J-K. Peir, and S. Lu, 35th IEEE Int'l
Performance Computing and Communication Conf. (IPCCC). Dec.
“Auther Retrospective: Bloom Filtering Cache Misses
for Accurate Data Speculation and Prefetching”,
Jih-Kwon Peir, S. Lai, S. Lu, J. Stark, and K. Lai, 25
years of ACM Int'l Conf. on Supercomputing (ICS), Dec.
“Guided Multiple Hashing: Achieving Perfect Balance
with Fast Lookup”,
X. Tao, Y. Qiao, J-K. Peir, S. Chen, Z. Huang, and S. Liu,
21st IEEE Int'l Conf. on Network Protocols (ICNP), Oct.
“Guided Region-Based GPU Scheduling: Utilizing
Multi-thread Parallelism to Hide Memory Latency”,
Jianmin Chen, Xi Tao, Zhen Yang, Jih-Kwon Peir, Xiaoyuan Li,
Shih-Lien Lu, 27th IEEE Int'l Parallel &
Distributed Processing Symp. (IPDPS), May 2013.
“Miss-Correlation Folding: Encoding Per-Block Miss Correlations in
Compressed DRAM for Data Prefetching”,
G. Liu, J-K. Peir, V. Lee,
26th IEEE Int'l
Parallel & Distributed Processing Symp. (IPDPS),
“Tree Structured Analysis on GPU Power Study”,
J. Chen, B. Li, Y. Zhang, L. Peng, J-K. Peir, Int'l Conf.
on Computer Design (ICCD),
a Compact Spread Estimator in Small High-Speed Memory", M. Yoon,
T. Li, S. Chen, J-K. Peir,
IEEE/ACM Trans. on Networking,
“Approximately-Perfect Hashing: Improving Network Throughput
through Efficient Off-chip Routing Table Lookup”, Z. Huang, J-K.
Peir, S. Chen, 30th IEEE
Int’l Conf. on Computer Communications, (INFOCOM), May
“Fast Routing Table Lookup Based on Deterministic
Multi-hashing,” Z. Huang,
D. Lin, S. Chen, J-K. Peir, S. IftekharulAlam, 18th IEEE Int’l
Conf. on Network Protocols (ICNP), Oct. 2010.
“Weak Execution Ordering - Exploiting Iterative Methods on
Many-Core GPUs,” J.
Chen, Z. Zuang, J.-K Peir, J. Chen, Z, Huang, F. Su, J-K. Peir,
J. Ho, IEEE Int’l Symp. on Performance Analysis of Systems and
Software (ISPASS), March 2010.
and Stack Simulation of CMP Caches," X. Shi, F.
Su, J-K. Peir, Y. Xia, Z. Yang, IEEE
Trans. on Parallel and Distributed Systems, Dec., 2009.
a Spread Estimator in a Small Memory," M.K. Yoon, T. Li, S.
Chen, J-K. Peir,
The 28th Conference on Computer Communications, (INFOCOM), April 2009.
vs. Capacity: Modeling and Single-Pass Stack Simulation on CMP
Caches,” X. Shi,, F. Su, J-K. Peir, Y. Xia, Z. Yang, 2007
IEEE Int'l Symp. on Performance Analysis of Systems and Software
(ISPASS), April 2007.
- “Overlapping Dependent Loads with Addressless Preload,” Z. Yang, X Shi, F
Su, J-K. Peir, The IEEE/ACM 15th Int'l Conf. on Parallel Architectures and
Compilation Techniques (PACT), Sep. 2006.
- "Coterminous Locality and Coterminous Group Data Prefetching on
Chip-Multiprocessors," X. Shi, Z. Yang, J-K. Peir, L. Peng,
Y. Chen, V. Lee, and B. Liang, 20th IEEE Int'l Parallel &
Distributed Processing Symp. (IPDPS), April 2006.
- "Signature Buffer: Bridging Performance Gap between Registers
and Caches," L. Peng, J-K. Peir, and K. Lai, 10th Int'l
Symp. on High Performance Computer Architecture (HPCA), Feb.
2004, pp. 164-175.
- "Address-Free Memory Access Based on Program Syntax Correlation
of Loads and Stores," L. Peng, J-K. Peir, Q. Ma, and K.
Lai, IEEE Transactions on VLSI Systems, Vol. 11(3), June
2003, pp. 314-324.
- "Bloom Filtering Cache Miss for Accurate Data Speculation and
Prefetching," J-K. Peir, S. Lai, S. LU, J. Stark, and K.
Lai, 2002 Int'l Conf. on Supercomputing (ICS), June 2002,
- "Direct Load: Dependence-Linked Dataflow Resolution of Load
Address and Cache Coordinate," B. Chung, J. Zhang, J-K.
Peir, S. Lai, K. Lai, 34th Int'l Symp. on Microarchitecture
(MICRO), Dec. 2001, pp. 76-87.
- "Symbolic Cache: Fast Memory Access Based on Program Syntax
Correlation of Loads and Stores," Q. Ma, J-K. Peir, L. Peng,
and K. Lai, 2001 Int'l Conf. on Computer Design (ICCD),
Sep. 2001, pp. 54-61.
- "Functional Implementation Techniques for CPU Cache
Memories," J-K. Peir, W. Hsu, and A. Smith, IEEE
Transactions on Computers, Special Issue on Cache Memory and
Related Problems, Vol. 48(2), Feb. 1999, pp. 100-110.
"Capturing Dynamic Memory Reference Behavior with
Adaptive Cache Topology," J-K. Peir, Y. Lee, and W. Hsu, 8th
Int'l Conf. on Architectural
Support for Programming Languages and Operating Systems (ASPLOS), Oct. 1998, pp. 240-250.
- CAREER Award, National Science Fundation, 1996
- IBM Faculty Research Development Partnership Award, 1995
- Two Best Paper Awards, IEEE Int'l Conf. on Computer Design,
- IBM Invention Achievement Award, 1992
- Associate Editors IEEE Trans. on Parallel and Distributed
Systems, and Journal of Parallel and Distributed Computing