Decoupling and Reforming Tag and Data Arrays for High-Performance Memory Hierarchy Systems

Sponsor: NSF CAREER Program

Abstract:

We investigate issues in memory hierarchy design and propose solutions to bridge the increasing performance gap between the processor and memory. First, we observe that the time needed to perform cache tag access/comparison and that needed to access cache data are not equal. This path imbalance can be exploited to achieve a more performance optimal cache design. The basic idea is to use an additional tag array to record the status and location of the recently used lines in the cache data array. By recording the cache line locations in this subset of the tag array, the data access is decoupled from the tag access/comparison path for a shorter overall cache access time. Second, in a multiprocessor system, cache coherence activities incur extra traffic to the heavily-loaded snooping bus and impose additional latency in accessing the data. By observing that references to the same memory location are often ordered at the software level, frequently rendering cache coherence activities are unnecessary and can be deferred until at the proper synchronization point.

Published Papers:

  1. J-K. Peir, W. W. Hsu, H. Young, and S. Ong, Improving Cache Performance with Balanced Tag and Data Paths, Proc. 7th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, Oct. 1996, pp. 268-278.
  2. J-K. Peir, W. W. Hsu, H. Young, and S. Ong, Fast Cache Access with Full-Map Block Directory, Proc. IEEE Int'l Conf. on Computer Designs, Austin, TX, Oct. 1997, pp. 578-586.
  3. B-K. Chung and J-K. Peir, LRU-Based Column-Associative Caches,
  4. J-K. Peir, Y. Lee, and W. W. Hsu, Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology, Proc. 8th Int'l Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, Oct. 1998, pp. 240-251.
  5. J-K. Peir, W. W. Hsu, and A. J. Smith Functional Implementation Techniques for CPU Cache Memories, IEEE Transactions on Computers, Vol. 48(2), Feb. 1999.
  6. J-K. Peir, W. W. Hsu, H. Young, and S. Ong Improving Cache Performance with Full-Map Block Directory, Journal of System Architecture, 2000.