Faculty & Staff

University of Florida

Computer and Information Science and Engineering

Jih-Kwon Peir

Associate Professor

Mailing Address:	301 CSE, P.O. Box 116120 Department of CISE University of Florida Gainesville, FL 32611
Office Location:	E354 CSE
Office Phone:	(352) 392-1044
Departmental FAX:	(352) 392-1220
Email:	peir@cise.ufl.edu
Website:	http://www.cise.ufl.edu/~peir

PhD. University of Illinois, 1986

Semester	Number	Title
Spring 06	CDA6159	High-Performance Computer Architecture
Fall 05	CDA5155	Computer Architecture Principles

Studies of Memory Performance of Multithreaded Multimedia Workloads, Sponsor: Microcomputer Research Lab, Intel Corp.
Predictive Multiprocessor Caching Techniques Based on Cache Interference and Working Set Change, Sponsor: NSF-CISE/EIA.
S-COMA Based DSM Architecture with Integrated on-Die Memory, Sponsor: Microcomputer Research Lab, Intel Corp.
Decoupling and Reforming Tag and Data Arrays for High-Performance Memory Hierarchy Systems, Sponsor: NSF/CAREER Program.
A Framework for Matching Applications with Parallel Machines, Sponsor: US Army Engineering Waterways Experiment Station.
Undergraduate Laboratory Development for Computer Architecture and Real-Timed Embedded Systems, Sponser: NSF Instrument and Laboratory Program.
Performance Studies of Symmetric Multiprocessor Systems, Sponsor: IBM Research Partnership Program.
Studying Application Program Behaviors on Affordable PCs.

"Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors," X. Shi, Z. Yang, J-K. Peir, L. Peng, Y. Chen, V. Lee, and B. Liang, 20th IEEE Int'l Parallel & Distributed Processing Symp., April 2006, to appear.
"Signature Buffer: Bridging Performance Gap between Registers and Caches," L. Peng, J-K. Peir, and K. Lai, 10th Int'l Symp. on High Performance Computer Architecture (HPCA-10), Feb. 2004, pp. 164-175.
"Address-Free Memory Access Based on Program Syntax Correlation of Loads and Stores," L. Peng, J-K. Peir, Q. Ma, and K. Lai, IEEE Transactions on VLSI Systems, Vol. 11(3), June 2003, pp. 314-324.
"Bloom Filtering Cache Miss for Accurate Data Speculation and Prefetching," J-K. Peir, S. Lai, S. LU, J. Stark, and K. Lai, 2002 Int'l Conf. on Supercomputing (ICS), June 2002, pp. 189-198.
"Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate," B. Chung, J. Zhang, J-K. Peir, S. Lai, K. Lai, 34th Int'l Symp. on Microarchitecture (MICRO), Dec. 2001, pp. 76-87.
"Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores," Q. Ma, J-K. Peir, L. Peng, and K. Lai, 2001 Int'l Conf. on Computer Design (ICCD), Sep. 2001, pp. 54-61.
"Improving Cache Performance with Full-Map Directory," J-K. Peir, W. Hsu, H. Young, and S. Ong, Journal of Microprocessing and Microprogramming, Vol. 46(5), March 2000, pp. 439-454.
"Functional Implementation Techniques for CPU Cache Memories," J-K. Peir, W. Hsu, and A. Smith, IEEE Transactions on Computers, Special Issue on Cache Memory and Related Problems, Vol. 48(2), Feb. 1999, pp. 100-110.
"Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology," J-K. Peir, Y. Lee, and W. Hsu, 8th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct. 1998, pp. 240-250.

CAREER Award, National Science Fundation, 1996
IBM Faculty Research Development Partnership Award, 1995
Two Best Paper Awards, IEEE Int'l Conf. on Computer Design, 1990, 2001
IBM Invention Achievement Award, 1992
Associate Editors, IEEE Trans. on Parallel and Distributed Systems, Journal of Parallel and Distributed Computing