Authors:    Farimah Farahmandi, Yuanwen Huang and Prabhat Mishra Publisher:   Springer, 2019 ISBN:   TBD Contents:      Part I: Introduction        System-on-Chip Security Vulnerabilities        SoC Security Verification Challenges        SoC Trust Metrics and Benchmarks    Part II: Security Verification using Formal Methods        Anomaly Detection using Symbolic Algebra        Trojan Localization using Symbolic Algebra        Vulnerability Assessment of Controller Designs        SoC Trust Validation using Security Properties    Part III: Security Validation using Simulation and Learning Techniques        Automated Test Generation for Detection of Malicious Functionality        Trojan Detection using Machine Learning    Part IV: Security Validation using Side-CHannel Analysis        Trojan Detection using Side-Channel Analysis        Detection of Hardware Trojans using Delay Analysis    Part V: Conclusions         The Future of Security Validation and Verification

System-on-Chip (SoC) is the brain behind the computing devices today. Unlike microcontroller based designs in the past, even resource constrained Internet-of-Things (IoT) devices nowadays incorporate one or more complex SoCs. A typical SoC consists of multiple Intellectual Property (IP) cores including processor, memory, network-on-chip, controllers, converters, input/output devices, etc. Drastic increase in SoC complexity has led to significant increase in SoC design and validation complexity. Reusable hardware IP based SoC design has emerged as a pervasive design practice in the industry to dramatically reduce design and verification cost while meeting aggressive time-to-market constraints. Growing reliance on these pre-verified hardware IPs, often gathered from untrusted third-party vendors, severely affects the security and trustworthiness of SoC computing platforms. Hardware-level vulnerabilities should be fixed before deployment since it affects the overall system security. Based on Common Vulnerability Exposure (CVE-MITRE) estimates, if hardware-level vulnerabilities are removed, the overall system vulnerability will reduce by 43%. Given the widespread acceptance of SoC designs in the electronic industry, it is critical to ensure their correctness from both functional and security perspectives.

This book provides an overview of SoC security vulnerabilities and associated security validation and verification challenges. The readers will gain a comprehensive understanding of the state-of-the-art SoC security validation and verification techniques using an effective combination of formal verification, machine learning, simulation-based validation as well as side-channel analysis. This book serves as a single-source of reference for students, researchers, designers and practitioners for designing secure, reliable and trustworthy SoCs.