Note: Reading assignments denoted by "Text n.m" denote Chapter n, Section m from
the required textbook (Patterson & Hennesey 1998).
DATES WEEK WEB MATERIAL COVERED IN CLASS ASSIGNMENTS
------- ---- ---------- -------------------------------- -------------------------
1/08-11 W1 Web AppxB W: Intro to Comp Organization Get Textbook, CISE Acct.
Web 1.1-3 F: Technology Trends Text 1.1-5
1/14-18 W2 Web 1.4 M: Logic Design ASN:Hw-1, Text 1.8, Appx.B
Web 1.4 W: Logic Design and Usage Text Appx. C
Web 1.5 F: Performance Assessment Text 2.1-5
1/21-25 W3 ---- M: MARTIN LUTHER KING HOLIDAY No Class
Web 1.6 W: Benchmarking Quiz #1 (Logic&Perf)
Web 1.6 F: Practical Benchmarks,ISA Text 2.6-9
1/28-2/1 W4 Web 2.1 M: ISA and Machine Language DUE:Hw-1, Text 3.1-3
Web 2.2 W: MIPS Instruction Format ASN:Hw-2, Text 3.4, Appx.A
Web 2.3 F: Decision Instructions Text 3.5
2/04-08 W5 Web 2.3 M: Procedure Support in MIPS Text 3.6-9, 4.1-2
Web 2.4 W: Number Systems and Datatypes Quiz #2 (MIPS Instr.)
Web 2.4 F: Datatypes and Addressing Text 3.9-10
2/11-15 W6 Web 2.6 M: Pointers and Arrays Text 3.11
Web 2.5 W: MIPS Programs, Exam-1 Review Text 3.12
Web 2.1 F: More on ISAs, Exam-1 Review DUE:Hw-2, Text 3.13
2/18-22 W7 ---- M: Exam 1, NRN 137, 8:20pm - 10:10pm - No Readings -
Web 3.1 W: Arithmetic/Logic Operations ASN:Hw-3, Text 4.1-2
Web 3.2 F: Arithmetic Logic Units (ALUs) Text 4.3-5
2/25-3/1 W8 Web 3.2-3 M: MIPS ALU and Boolean Multipl'n. Text 4.5-7
Web 3.3-4 W: Boolean Division, Floating Point Quiz #3 (ALUs)
Web 3.4 F: IEEE 754 and MIPS Floating Point DUE:Hw-3, Text 4.8-10
---- SPRING BREAK 2-9 March 2002 ----
3/11-15 W10 Web 4.1 M: CPU - Control & Dataflow, Design Text 5.1-3
Web 4.2 W: Datapath Design, Single-Cycle DPs ASN:Hw-4, Text 5.3
Web 4.3 F: Multi-Cycle Datapaths Text 5.4
3/18-22 W11 Web 4.3 M: Datapaths and Controller FSM Text 5.4-5
Web 4.4 W: Microprogramming Quiz #4 (Mult,Div)
Web 4.4 F: Microprogramming, Ex2 Rvw Text 5.6
3/25-29 W12 ---- M: Exam 2, NRN 137, Periods E2-E3
Web 5.1-2 W: Pipelined Datapaths & Control Text 6.1-2
Web 5.2-3 F: Pipelined Control DUE:Hw-4 Text 6.2-3
4/01-05 W13 Web 5.2-3 M: Introduction to Pipeline Hazards Text 6.3
Web 5.2-3 W: Pipeline Hazards & Exceptions ASN: Hw-5, Text 6.4-6
Web 5.4 F: Pipeline Performance Analysis Text 6.5-7
4/08-12 W14 Web 6.1-2 M: Memory Hierarchies, Cache Text 7.1-7.2
Web 6.3 W: Cache Performance Analysis Quiz #5 (Pipelines)
Web 6.3 F: More Cache Performance Analysis Text 7.3
4/15-19 W15 Web 6.2 M: Virtual Memory Text 7.4
Web 6.3 W: Memory Systems Performance DUE: Hw-5, Text 7.5-7.7
Web 6.4 F: I/O Devices and Requirements Text 8.1-8.3
4/22-24 W16 Web 6.4 M: I/O and Buses, Final Exam Review Text 8.4-8.5
Web 6.4 W: I/O Performance Analysis Text 8.6-8
4/30 FIN ---- T: FINAL EXAM, CSE/A101, Tue 30 Apr: 12.30-2.30pm
This concludes the description of the anticipated class schedule. Use the E-mail links at the top of this Web page to correspond with the instructor or TAs, if you have any questions.