RevComp - The Reversible and Quantum Computing Research Group
Reversible/Adiabatic Chips: Tick, FlatTop, XRAM, Pendulum
These four pioneering reversible/adiabatic chips were designed by the MIT Reversible Computing research group, by a team of graduate and undergraduate students including then-PhD-student Michael Frank, who now heads the UF Reversible & Quantum Computing research group.

The Reversible & Quantum Computing Research Group, based at the University of Florida's CISE and ECE departments, studies all aspects of reversible computing - from basic science to practical engineering, and from fundamental physics to high-level distributed software applications.  The RevComp group's background includes the development of these four pioneering reversible CMOS chips in earlier work done at MIT.  (See here for higher-resolution chip photos.)
What's Reversible Computing?
    Broadly speaking, there are two different levels of reversible computing: Logically reversible computing means computing in such a way that it always remains possible to efficiently reconstruct the previous state of the computation from the current state. (Follow the above link for more details.) Doing this enables thermodynamically reversible computing which generates no (or very little) new physical entropy, and is thus energy efficient.  There are a variety of thermodynamically reversible, energy-recovering logic circuit techniques that exist or have been proposed.  See this link for a more recent, 7-paragraph overview.
Graph: Cost-Efficiency Advantages of Reversible Computing in Future Decades
Results from a detailed numerical model of cost-efficiency of reversible versus irreversible computers in future generations of technology. The cost-efficiency of irreversible computing eventually hits a thermodynamic brick wall, and cannot improve further as long as the cost of energy (and/or the heat flux limit of the cooling technology) is fixed. In contrast, the cost-efficiency of reversible computing can continue to improve far beyond this point, limited only by achievable energy leakage rates, which have no known fundamental lower limit. (However, for generating this graph, an arbitrary lower limit of 1 kT/ms/bit-device was assumed.) Note that the advantages of reversible computing could rise to 1,000-100,000x by the 2050s. This model even takes into account the algorithmic overheads of reversibility and the proportionality of energy dissipation to speed in adiabatic processes. These results were first published in Michael P. Frank, "Nanocomputer Systems Engineering" (.doc,.ps), 2003 Nanotechnology Conference & Trade Show, Feb. 23-27, 2003, San Francisco, CA.