Research
The focus of Embedded System Lab is the development of tools, techniques and methodologies for system level modeling, design space exploration, functional test generation, retargetable simulation, architecture synthesis, lossless compression, real-time scheduling, dynamic reconfiguration, and functional verification of embedded and reconfigurable systems.

Research Interests
Embedded Systems: system-level modeling, exploration, HW/SW partitioning, validation and code compression.
Hardware Verification: validation using a combination of simulation based techniques and formal methods.
VLSI CAD: fast and retargetable simulation, high-level synthesis and test generation.
Computer Architecture: processor validation, instruction-set simulation, high-level estimation and evaluation.
Design and Verification of Dynamic Reconfigurations in Real-time Systems.


Ongoing Research Projects

  Title   Sponsors   Funding   Duration
Functional Verification of Multicore Architectures   NSF (CAREER)   $400,000   2008 - 2013
Integration of Lossless Compression and Embedded Encryption   NSF (Core-CSR)   $100,000   2009 - 2011
SOC Validation using SystemC Transaction Level Models   Intel Corporation   $120,000   2006 - 2009
Scheduling-Aware Dynamic Reconfigurations   NSF+SRC (MCDA)   $300,000   2009 - 2012

Current Students

Ph.D. Students

 
Your Name
Ph.D. Student
Research Area: Embedded Systems
Prerequisites: Please read this before you contact me.

 
Kanad Basu
Ph.D. Student
Research Area: Nano-CMOS Architectures
Recent Publications: IEEE TVLSI 2009, GLSVLSI 2008.
Major Awards: CISE Department Travel Grant.
Homepage: http://www.cise.ufl.edu/~kbasu

 
Mingsong Chen
Ph.D. Student
Research Area: High-Level Executable Specifications
Recent Publications: IEEE TCAD 2009, DATE 2010, VLSI 2010, VLSI 2009, GLSVLSI 2008, HLDVT 2007.
Major Awards: DAC Young Student Support Program Award.
Homepage: http://www.cise.ufl.edu/~mchen

  Xiaoke Qin
Ph.D. Student
Research Area: Dynamic Reconfigurable Architectures
Recent Publications: DATE 2010, IEEE TVLSI 2009, VLSI 2010, IEEE TCAD 2009, VLSI 2009.
Major Awards: DAC Young Student Support Program Award.
Homepage: http://www.cise.ufl.edu/~xqin

  Weixun Wang
Ph.D. Student
Research Area: Scheduling-Aware Reconfiguration Techniques
Recent Publications: VLSI 2010, ISVLSI 2009, VLSI 2009.
Major Awards: CISE Department Travel Grant.
Homepage: http://www.cise.ufl.edu/~wewang


M.S. Students

 
Kartik Shrivastava
M.S. Student
MS Thesis: Synergistic Integration of Encryption and Compression in Embedded Systems
Homepage: http://www.cise.ufl.edu/~kshrivas

Graduated Students

Ph.D. Students

  Heon-Mo Koo
Ph.D., December 2007
PhD Thesis: Coverage-driven Test Generation for Functional Validation of Pipelined Processors.
Recent Publications: ACM TECS 2009, CODES+ISSS 2008, UKC 2007, DATE 2006, GLSVLSI 2006, UKC 2006, MTV 2006, MTV 2005.
Major Awards: KUSCO-KSEA Scholarship, Korean Graduate Student Award.
First Position: Intel Corporation, Folsom, California.


M.S. Students

 
Chetan Murthy
MS, December 2008
MS Thesis: Decoding-Aware Compression Techniques for Reconfigurable Systems.
Recent Publications: IEEE TVLSI 2009, ISVLSI 2009, GLSVLSI 2009.
First Position: Member Technical Staff, Juniper Networks, Sunnyvale, California.

 
Seok-Won Seong
MS, May 2006
MS Thesis: Dictionary-Based Code Compression Techniques using Bit-Masks for Embedded Systems.
Recent Publications: IEEE TCAD 2008, DATE 2007 and ICCAD 2006.
First Position: IT Specialist, IBM New York.
Current Position: Graduate Student, Stanford University.


Other Students (Lab Alumni)

Research Overview

Specification-driven Validation:   One of the most important problems in today's microprocessor design verification is the lack of a golden reference model that can be used for verifying the design at different levels of abstraction. Thus many existing validation techniques employ a bottom-up approach to pipeline verification, where the functionality of an existing pipelined processor is, in essence, reverse-engineered from its RT-level implementation. Our verification technique is complimentary to these bottom up approaches. Our approach leverages the system architects knowledge about the behavior of the pipelined processor, through Architecture Description Language (ADL) constructs, and thus allows a powerful top-down approach to pipeline verification. We validate the ADL specification. The validated specification is used as a golden reference model for test generation, equivalence checking, and functional validation of embedded systems. Publications

Functional Test Generation:   Functional verification is widely acknowledged as a major bottleneck in microprocessor design. While early work on specification driven functional test program generation has proposed several promising ideas, many challenges remain in applying them to realistic embedded processors. We present a graph coverage based functional test program generation approach for pipelined processors. The proposed methodology makes three important contributions. First, it automatically generates the graph model of the pipelined processor from the specification using functional abstraction. Second, it generates functional test programs based on the coverage of the pipeline behavior. Finally, the test generation time is drastically reduced due to the use of decompositional model checking. Publications

Dynamic Reconfigurations: Dynamic reconfiguration techniques are widely used for designing efficient System-on-Chip (SOC) architectures. Many promising reconfiguration methods exist including dynamic reconfiguration of caches, memory hierarchies, and communication architectures to improve both energy consumption and overall performance in SOC architectures. Although, these techniques have received considerable attention from various domains in recent years, dynamic reconfiguration techniques are not employed in real-time systems. This is due to the fact that many cyber physical systems consist of tasks with real-time constraints, and the additional computation required for dynamic reconfiguration may adversely affect the critical tasks. The problem is further aggravated in the presence of aperiodic tasks where task arrival cannot be predicted prior to execution. Missing deadlines may lead to catastrophic effects in many safety-critical systems. The goal of this proposal is to exploit the advantages of dynamic reconfigurations in cyber physical systems without compromising real-time constraints. Publications

Lossless Compression:   Embedded systems are constrained by the available memory. Code compression techniques address this issue by reducing the code size of application programs. Dictionary-based code compression techniques are popular because they offer both good compression ratio and fast decompression scheme. Various techniques improve standard dictionary-based compression by considering mismatches. The goal of this work is to provide a cost-benefit analysis framework for improving the compression ratio by creating more matching patterns, and to develop an efficient code compression technique using bitmasks to improve the compression ratio without introducing any decompression penalty. Publications

Design Space Exploration:   Embedded systems present a tremendous opportunity to customize the designs by exploiting the application behavior. Recent work on language-driven exploration uses Architectural Description Languages (ADL) to capture the architecture, generate automatically a software toolkit (including compiler, simulator, assembler) for that architecture, and provide feedback to the designer on the quality of the architecture. While contemporary ADLs can effectively capture one class of architecture, they are typically unable to capture a wide spectrum of processor and memory features present in DSP, VLIW, EPIC and Superscalar processors. Our approach allows explicit specification of heterogeneous architectures and permits co-exploration of the processor, co-processor and memory subsystem for a wide variety of programmable embedded systems. Publications

Architecture Synthesis:   As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques to rapidly explore and evaluate candidate architectures based on area, power, and performance constraints. This requires automatic generation of hardware implementation from the specification. We have developed a functional abstraction based framework to generate synthesizable RTL from the ADL specification. Our framework allows varied micro-architectural modifications, such as, addition of pipeline stages, pipeline paths, opcodes and new functional units. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude. Publications