Publications

Disclaimer: The following publications are covered by copyright. Permission to make digital/hard copy of all or part of the following papers, technical reports, and presentations for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage. To copy otherwise, to republish, to post on servers, or to redistribute to lists requires prior specific permission.
Upcoming Conferences:   Click here     

Book

B2 Prabhat Mishra and Nikil Dutt (Editors), Processor Description Languages - Applications and Methodologies, Morgan Kaufmann, ISBN: 978-0-12-374287-2, June 2008.
B1 Prabhat Mishra and Nikil Dutt, Functional Verification of Programmable Embedded Architectures - A Top-Down Approach, Springer, ISBN: 0-387-26143-5, July 2005.

Ph.D. Dissertations

D2 Heon-Mo Koo, Coverage-driven test Generation for Functional Validation of Pipelined Processors, Ph.D. Thesis, University of Florida, December 2008.
D1 Prabhat Mishra, Specification-driven Validation of Programmable Embedded Systems, Ph.D. Thesis, University of California, Irvine, March 2004. EDAA Outstanding Dissertation Award 2004.

M.S. Theses

T3 Chetan Murthy, Decoding-Aware Compression Techniques for Reconfigurable Systems, MS Thesis, University of Florida, December 2008.
T3 Yogesh Sharma, Integration of Code Compression and Encryption in Embedded Systems, MS Thesis, University of Florida, December 2008.
T2 Seok-Won Seong, Dictionary-based Code Compression Techniques using Bitmasks for Embedded Systems, MS Thesis, University of Florida, April 2006.
T1 Prabhat Mishra, Illumination Modeling with Reflections, M.Tech. Thesis, Indian Institute of Technology, Kharagpur, January 1996.

Journal Articles

J16 Xiaoke Qin, Chetan Murthy and Prabhat Mishra, Decoding-aware Compression of FPGA Bitstreams, Accepted to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2009.
J15 Mingsong Chen and Prabhat Mishra, Functional Test Generation using Efficient Property Clustering and Learning Techniques, Accepted to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2009.
J14 Kanad Basu and Prabhat Mishra, Test Data Compression using Efficient Bitmask and Dictionary Selection Methods, Accepted to appear in IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2009.
J13 Xiaoke Qin and Prabhat Mishra, A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 28, no 8, pages 1224-1236, August 2009.
J12 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Design and Property Decomposition Techniques, ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 4, article 32, July 2009.
J11 Seok-Won Seong and Prabhat Mishra, Bitmask-Based Code Compression for Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), volume 27, no 4, pages 673-685, April 2008.
J10 Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Hybrid Compiled Simulation: An Efficient Technique for Instruction-Set Architecture Simulation, Accepted to appear in ACM Transactions on Embedded Computing Systems (TECS), volume 8, no 3, 27 pages, Article 20, April 2009.
J9 Prabhat Mishra and Nikil Dutt, Specification-driven Directed Test Generation for Validation of Pipelined Processors, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 13, no 2, 36 pages, article 42, July 2008.
J8 Prabhat Mishra, Aviral Shrivastava, and Nikil Dutt, Architecture Description Language (ADL)-driven Software Toolkit generation for Architectural Exploration of Programmable SOCs, ACM Transactions on Design Automation of Electronic Systems (TODAES), volume 11, no 3, pages 1-33, July 2006.
J7 Mehrdad Reshadi, Prabhat Mishra and Nikil Dutt, A Retargetable Framework for Instruction-Set Architecture Simulation, ACM Transactions on Embedded Computing Systems (TECS), volume 5, no 2, pages 431-452, May 2006.
J6 Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, and Magdy Abadir, A Methodology for Validation of Microprocessors using Symbolic Simulation, Inderscience International Journal of Embedded Systems (IJES), volume 1, no 1/2, pages 14-22, 2005.
J5 Prabhat Mishra and Nikil Dutt, Architecture Description Languages for Programmable Embedded Systems, IEE Proceedings on Computers and Digital Techniques (CDT), Special issue on Embedded Microelectronic Systems: Status and Trends, volume 152, no 3, pages 285--297, May 2005.
J4 Prabhat Mishra, Mahesh Mamidipaka and Nikil Dutt, Processor-Memory Co-Exploration using an Architecture Description Language, ACM Transactions on Embedded Computing Systems (TECS), volume 3, number 1, pages 140-162, February 2004.
J3 Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, and Magdy Abadir, A Top-Down Methodology for Validation of Microprocessors, IEEE Design and Test of Computers (Design&Test), Special Issue on Functional Verification and Testbench Generation, volume 21, number 2, pages 122-131, 2004.
J2 Prabhat Mishra and Nikil Dutt, Modeling and Validation of Pipeline Specifications, ACM Transactions on Embedded Computing Systems (TECS), volume 3, number 1, pages 114-139, February 2004.
J1 Prabhat Mishra, Nikil Dutt, and Hiroyuki Tomiyama, Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications, Kluwer Design Automation for Embedded Systems (DAES), volume 8, number 2, pages 249-265, 2003.

Patents

P1 Prabhat Mishra and Nikil Dutt, Functional Coverage driven Test Generation for Validation of Pipelined Processors, US Patent 7533294, May 12, 2009.
P2 Prabhat Mishra and Seok-won Seong, Bitmaksk-based Code Compression Technique and Decompression Mechanism, Provisional Patent UF 12654, 2007.

Book Chapters

BC8 Nirmalya Bandyopadhyay, Kanad Basu and Prabhat Mishra, HMDES, ISDL and Other Contemporary ADLs, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC7 Prabhat Mishra and Nikil Dutt, EXPRESSION: An ADL for Software Toolkit Generation, Exploration, and Validation of Programmable SOC Architectures, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC6 Prabhat Mishra and Aviral Shrivastava, ADL-driven Methodologies for Design Automation of Embedded Processors, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC5 Prabhat Mishra and Nikil Dutt, Introduction to Architecture Descripton Languages, Processor Description Languages: Applications and Methodologies, Prabhat Mishra and Nikil Dutt, Editors, Morgan Kaufmann Publishers, 2008.
BC4 Prabhat Mishra and Nikil Dutt, Architecture Description Languages, Customizable and Configurable Embedded Processors, Paolo Ienne and Rainer Leupers, Editors, Morgan Kaufmann Publishers, 2006.
BC3 Prabhat Mishra and Nikil Dutt, Processor Modelling and Design Tools, The EDA Handbook, G. Martin, L. Lavagno, and L. Scheffer, Editors, CRC Press, 2005.
BC2 Prabhat Mishra and Nikil Dutt, Architecture Description Languages for Programmable Embedded Systems, System On Chip: Next Generation Electronics, Bashir M. Al-Hashimi, Editor, IEE Press, 2005.
BC1 Prabhat Mishra and Nikil Dutt, Modeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions, in Design and Analysis of Distributed Embedded Systems, Bernd Kleinjohann et al., Editors, Kluwer Academic Publishers, 2002, pp. 81-90.

Referred Conference Papers

C31 Mingsong Chen, Xiaoke Qin and Prabhat Mishra, Efficient Decision Ordering Techniques for SAT-based Test Generation, Design Automation and Test in Europe (DATE), pages -, Dresden, Germany, March 8 - 12, 2010.
C30 Xiaoke Qin, Mingsong Chen and Prabhat Mishra, Synchronized Generation of Directed Tests using Satisfiability Solving, International Conference on VLSI Design, pages -, Bangalore, India, January 3-7, 2010.
C29 Weixun Wang and Prabhat Mishra, Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache Reconfiguration in Real-Time Systems, International Conference on VLSI Design, pages -, Bangalore, India, January 3-7, 2010.
C28 Nga Dang, Abhik Roychoudhury, Tulika Mitra and Prabhat Mishra, Generating Test Programs to Cover Pipeline Interactions, Accepted to appear in ACM/IEEE Design Automation Conference (DAC), pages -, San Francisco, California, USA, July 26-31, 2009. Nominated for Best Paper Award
C27 Weixun Wang and Prabhat Mishra, Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems, IEEE International Symposium on VLSI (ISVLSI), pages 145-150, Tampa, Florida, USA, May 13-15, 2009.
C26 Chetan Murthy and Prabhat Mishra, Lossless Compression using Efficient Encoding of Bitmasks, IEEE International Symposium on VLSI (ISVLSI), pages 163-168, Tampa, Florida, USA, May 13-15, 2009.
C25 Chetan Murthy and Prabhat Mishra, Bitmask-based Control Word Compression for NISC Architectures, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 321-326, Boston, USA, May 10-12, 2009.
C24 Xiaoke Qin and Prabhat Mishra, Efficient Placement of Compressed Code for Parallel Decompression, International Conference on VLSI Design, pages 335-340, New Delhi, India, January 5-9, 2009.
C23 Weixun Wang, Prabhat Mishra and Ann-Gordon Ross, SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems, International Conference on VLSI Design, pages 547-552, New Delhi, India, January 5-9, 2009.
C22 Prabhat Mishra and Mingsong Chen, Efficient Techniques for Directed Test Generation using Incremental Satisfiability, International Conference on VLSI Design, pages 65-70, New Delhi, India, January 5-9, 2009. Nominated for Best Paper Award
C21 Heon-Mo Koo and Prabhat Mishra, Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 137-142, Atlanta, USA, October 19 - 24, 2008.
C20 Kanad Basu and Prabhat Mishra, A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 83-88, Orlando, USA, May 4 - 6, 2008.
C19 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Coverage-driven Automatic Test Generation for UML Activity Diagrams, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 139-142, Orlando, USA, May 4 - 6, 2008.
C18 Seok-Won Seong and Prabhat Mishra, An Efficient Code Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods, Design Automation and Test in Europe (DATE), pages 582-587, Nice, France, April 16 - 20, 2007.
C17 Heon-Mo Koo and Prabhat Mishra, Automated Micro-architectural Test Generation for Validation of Modern Processors, US-Korea Conference on Global Challenges in Science and Technology (UKC), Washington DC, August 9-12, 2007.
C16 Xianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra and Xu Cheng, A Retargetable Software Timing Analyzer Using Architecture Description Language, Asia and South Pacific Design Automation Conference (ASPDAC), pages 396-401, Yokohama, Japan, January 23 - 26, 2007.
C15 Seok-Won Seong and Prabhat Mishra, A Bitmask-based Code Compression Technique for Embedded Systems, IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 251-254, San Jose, California, November 5 - 9, 2006.
C14 Heon-Mo Koo and Prabhat Mishra, Test Generation using SAT-based Bounded Model Checking for Validation of Pipelined Processor, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 362-365, Philadelphia, USA, April 30 - May 2, 2006.
C13 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using Property Decompositions for Validation of Pipelined Processors, Design Automation and Test in Europe (DATE), pages 1240-1245, Munich, Germany, March 6-10, 2006.
C12 Heon-Mo Koo and Prabhat Mishra, Coverage-driven Functional Test Generation for Processor Validation using Formal Methods, US-Korea Conference on Science, Technology, and Entrepreneurship (UKC), New Jersey, August 10-13, 2006.
C11 Mehrdad Reshadi and Prabhat Mishra, Memory Access Optimizations in Instruction-Set Simulators, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 237-242, New York, September 19-21, 2005.
C10 Prabhat Mishra and Nikil Dutt, Functional Coverage Driven Test Generation for Validation of Pipelined Processors, Design Automation and Test in Europe (DATE), pages 678-683, Munich, Germany, March 7-11, 2005.
C9 Prabhat Mishra and Nikil Dutt, Functional Validation of Programmable Architectures, EUROMICRO Symposium on Digital System Design (DSD), pages 12-19, Rennes, France, August 31 - September 3, 2004. Keynote Paper
C8 Prabhat Mishra and Nikil Dutt, Graph-based Functional Test Program Generation for Pipelined Processors, Design Automation and Test in Europe (DATE), pages 182-187, Paris, France, February 16-20, 2004.
C7 Prabhat Mishra, Arun Kejariwal, and Nikil Dutt, Synthesis-driven Exploration of Pipelined Embedded Processors, International Conference on VLSI Design, pages 921-926, Mumbai, India, January 5-9, 2004.
C6 Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, and Nikil Dutt, An Efficient Retargetable Framework for Instruction-Set Simulation, International Symposium on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pages 13-18, California, USA, October 1-3, 2003. Best Paper Award
C5 Mehrdad Reshadi, Prabhat Mishra, and Nikil Dutt, Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation, Design Automation Conference (DAC), pages 758-763, Anaheim, USA, June 2-6, 2003.
C4 Prabhat Mishra, Hiroyuki Tomiyama, Nikil Dutt, and Alex Nicolau, Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units, Design Automation and Test in Europe (DATE), pages 36-43, Paris, France, March 4-8, 2002.
C3 Prabhat Mishra, Hiroyuki Tomiyama, Ashok Halambi, Peter Grun, Nikil Dutt, and Alex Nicolau, Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language, Asia and South Pacific Design Automation Conference (ASPDAC) & VLSI Design, pages 458-463, Bangalore, India, January 7-11, 2002.
C2 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Functional Abstraction driven Design Space Exploration of Heterogeneous Programmable Architectures, International Symposium on System Synthesis (ISSS), Montreal, Canada, October 1-3, pages 256-261, 2001.
C1 Prabhat Mishra, Peter Grun, Nikil Dutt, and Alex Nicolau, Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language, International Conference on VLSI Design, pages 70-75, Bangalore, India, January 3-7, 2001.

Premier Referred Workshop Papers

W10 Mingsong Chen, Prabhat Mishra and Dhrubajyoti Kalita, Towards RTL Test Generation from SystemC TLM Specifications, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 91-96, Irvine, California, November 7-9, 2007.
W9 Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra and Magdy Abadir, Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 33-36, Austin, Texas, USA, December 4-5, 2006.
W8 Prabhat Mishra, Heon-Mo Koo, and Zhuo Huang, Language-driven Validation of Pipelined Processors using Satisfiability Solvers, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 119-126, Austin, Texas, USA, November 3-4, 2005.
W7 Prabhat Mishra, Nikil Dutt, and Yaron Kashai, Functional Verification of Pipelined Processors: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 79-84, Austin, USA, September 9-10, 2004.
W6 Prabhat Mishra, Arun Kejariwal and Nikil Dutt, Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models, IEEE International Workshop on Rapid System Prototyping (RSP), pages 226-232, San Diego, USA, June 9-11, 2003.
W5 Prabhat Mishra and Nikil Dutt, A Methodology for Validation of Microprocessors using Equivalence Checking, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages 83-88, Austin, USA, May 29-30, 2003.
W4 Prabhat Mishra and Nikil Dutt, Automatic Functional Test Program Generation for Pipelined Processors using Model Checking, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 99-103, Cannes, France, October 27-29, 2002.
W3 Prabhat Mishra, Narayanan Krishnamurthy, Nikil Dutt and Magdy Abadir, A Property Checking Approach to Microprocessor Verification using Symbolic Simulation, Microprocessor Test and Verification (MTV), Austin, Texas, June 6-7, 2002.
W2 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Automatic Validation of Pipeline Specifications, IEEE International High Level Design Validation and Test Workshop (HLDVT), pages 9-13, Monterey, California, November 7-9, 2001.
W1 Prabhat Mishra, Frederic Rousseau, Nikil Dutt, and Alex Nicolau, Architecture Description Language driven Design Space Exploration in the Presence of Coprocessors, Synthesis And System Integration of MIxed Technologies (SASIMI), Nara, Japan, October 18-19, 2001.

Magazine Articles

M1 Prabhat Mishra, Processor Validation: A Top-Down Approach, IEEE Potentials, February/March 2005.

Technical Reports

T20 Weixun Wang and Prabhat Mishra, A Partitioned Bitmask-based Technique for Lossless Seismic Data Compression, CISE Technical Report # 08-452, University of Florida, May 07, 2008.
T19 Cristobal Rivero and Prabhat Mishra, Lossless Audio Compression: A Case Study, CISE Technical Report # 08-415, University of Florida, August 07, 2008.
T18 Elias Baaklini, Tarek Kaissi and Prabhat Mishra, Peer-to-Peer Assisted Voice Communication using Cell Phones, CISE Technical Report # 05-005, University of Florida, 2005.
T17 Ryan Close and Prabhat Mishra, Power-Adaptive Routing Topology for Remote Sensor Networks, CISE Technical Report # 05-006, University of Florida, 2005.
T16 Zhuo Huang and Prabhat Mishra, SAT-based Combinational Equivalence Checking, CISE Technical Report # 05-007, University of Florida, 2005.
T15 Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using SAT-based Bounded Model Checking, CISE Technical Report # 05-008, University of Florida, 2005.
T14 Prabhat Mishra and Nikil Dutt, Functional Coverage Driven Test Generation for Validation of Pipelined Processors, CECS Technical Report # 04-05, University of California, Irvine, 2004.
T13 Prabhat Mishra, Nikil Dutt and Hiroyuki Tomiyama, Architecture Description Language driven Validation of Dynamic Behavior in Pipelined Processor Specifications, CECS Technical Report # 03-25, University of California, Irvine, 2003.
T12 S. Pasricha, P. Biswas, P. Mishra, A. Shrivastava, A. Mandal, N. Dutt and A. Nicolau, A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor, CECS Technical Report # 03-17, University of California, Irvine, 2003.
T11 Mehrdad Reshadi, Prabhat Mishra, Nikhil Bansal and Nikil Dutt, ReXSim: A Retargetable Framework for Instruction-Set Architecture Simulation., CECS Technical Report # 03-05, University of California, Irvine, 2003 [ Postscript , PDF ].
T10 Arun Kejariwal and Prabhat Mishra and Jonas Astrom and Nikil Dutt, HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors., CECS Technical Report # 03-04, University of California, Irvine, 2003 [ Postscript , PDF ].
T9 Prabhat Mishra and Nikil Dutt, Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV., CECS Technical Report # 02-26, University of California, Irvine, September 06, 2002 [ Postscript , PDF ].
T8 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Architecture Description Language driven Validation of Processor, Memory, and Co-Processor Pipelines, ICS Technical Report # 01-55, University of California, Irvine, July 2001 [ Postscript , PDF ].
T7 Prabhat Mishra, Hiroyuki Tomiyama, Nikil Dutt, and Alex Nicolau, Architecture Description Language driven Verification of In-Order Execution in Pipelined Processors, ICS Technical Report # 01-20, University of California, Irvine, May 2001 [ Postscript , PDF ].
T6 Prabhat Mishra, Mahesh Mamidipaka, and Nikil Dutt, A Framework for Memory Subsystem Exploration, CECS Technical Report # 02-19, University of California, Irvine, May 24, 2002 [ Postscript , PDF ].
T5 Prabhat Mishra, Frederic Rousseau, Nikil Dutt, and Alex Nicolau, Coprocessor Codesign for Programmable Architectures, ICS Technical Report # 01-13, University of California, Irvine, April 2001 [ Postscript , PDF ].
T4 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, A Study of Out-of-Order Completion for the MIPS R10K Superscalar Processor, ICS Technical Report # 01-06, University of California, Irvine, January 2001 [ Postscript , PDF ].
T3 Prabhat Mishra, Nikil Dutt, and Alex Nicolau, Specification of Hazards, Stalls, Interrupts, and Exceptions in EXPRESSION, ICS Technical Report # 01-05, University of California, Irvine, January 2001 [ Postscript , PDF ].
T2 Prabhat Mishra, Jonas Astrom, Nikil Dutt, and Alex Nicolau, Functional Abstraction of Programmable Embedded Systems, ICS Technical Report # 01-04, University of California, Irvine, January 2001 [ Postscript , PDF ].
T1 Prabhat Mishra, Peter Grun, Nikil Dutt, and Alex Nicolau, Memory Subsystem description in EXPRESSION, ICS Technical Report # 00-31, University of California, Irvine, October 2000 [ Postscript , PDF ].