Faculty & Staff

University of Florida

Computer and Information Science and Engineering

Jih-Kwon Peir

Associate Professor

Mailing Address:	301 CSE, P.O. Box 116120 Department of CISE University of Florida Gainesville, FL 32611
Office Location:	E354 CSE
Office Phone:	(352) 505-1573
Departmental FAX:	(352) 392-1220
Email:	peir@cise.ufl.edu
Website:	http://www.cise.ufl.edu/~peir

PhD. University of Illinois, 1986

Semester	Number	Title
Spring 2012	CIS6930	Special Topic: GPU Architecture and Programming
Fall 2012	CDA5155	Computer Architecture Principles

NeTS:Small:Making Online Network Functions Fast and Compact, Sponsor: NSF-CISE/CNF, 2011.
Memory Hierarchy Studies on Many-Core CMPs with Large On-Die Storage, Sponsor: Intel Corp, 2010.
Studies of Memory Performance of Multithreaded Multimedia Workloads, Sponsor: Microcomputer Research Lab, Intel Corp.
Predictive Multiprocessor Caching Techniques Based on Cache Interference and Working Set Change, Sponsor: NSF-CISE/EIA.
S-COMA Based DSM Architecture with Integrated on-Die Memory, Sponsor: Microcomputer Research Lab, Intel Corp.
Decoupling and Reforming Tag and Data Arrays for High-Performance Memory Hierarchy Systems, Sponsor: NSF/CAREER Program.
A Framework for Matching Applications with Parallel Machines, Sponsor: US Army Engineering Waterways Experiment Station.
Undergraduate Laboratory Development for Computer Architecture and Real-Timed Embedded Systems, Sponser: NSF Instrument and Laboratory Program.
Performance Studies of Symmetric Multiprocessor Systems, Sponsor: IBM Research Partnership Program.

“Miss-Correlation Folding: Encoding Per-Block Miss Correlations in Compressed DRAM for Data Prefetching”, G. Liu, J-K. Peir, V. Lee, 26th IEEE Int'l Parallel & Distributed Processing Symp. (IDPDS'12), May 2012.
“Tree Structured Analysis on GPU Power Study”, J. Chen, B. Li, Y. Zhang, L. Peng, J-K. Peir, Int'l Conf. on Computer Design (ICCD'11), Oct. 2011.
"Fit a Compact Spread Estimator in Small High-Speed Memory", M. Yoon, T. Li, S. Chen, J-K. Peir, IEEE/ACM Trans. on Networking, Oct. 2011.
“Approximately-Perfect Hashing: Improving Network Throughput through Efficient Off-chip Routing Table Lookup”, Z. Huang, J-K. Peir, S. Chen, 30th IEEE Int’l Conf. on Computer Communications, (INFOCOM’11), May 2011.
“Fast Routing Table Lookup Based on Deterministic Multi-hashing,” Z. Huang, D. Lin, S. Chen, J-K. Peir, S. IftekharulAlam, 18th IEEE Int’l Conf. on Network Protocols (ICNP’10), Oct. 2010.
“Weak Execution Ordering - Exploiting Iterative Methods on Many-Core GPUs,” J. Chen, Z. Zuang, J.-K Peir, J. Chen, Z, Huang, F. Su, J-K. Peir, J. Ho, IEEE Int’l Symp. on Performance Analysis of Systems and Software (ISPASS’10), March 2010.
"Modeling and Stack Simulation of CMP Caches," X. Shi, F. Su, J-K. Peir, Y. Xia, Z. Yang, IEEE Trans. on Parallel and Distributed Systems, Dec., 2009.
"Fitting a Spread Estimator in a Small Memory," M.K. Yoon, T. Li, S. Chen, J-K. Peir, The 28th Conference on Computer Communications, (INFOCOM'09), April 2009.
“Accessibility vs. Capacity: Modeling and Single-Pass Stack Simulation on CMP Caches,” X. Shi,, F. Su, J-K. Peir, Y. Xia, Z. Yang, 2007 IEEE Int'l Symp. on Performance Analysis of Systems and Software (ISPASS'07), April 2007.
“Overlapping Dependent Loads with Addressless Preload,” Z. Yang, X Shi, F Su, J-K. Peir, The IEEE/ACM 15th Int'l Conf. on Parallel Architectures and Compilation Techniques (PACT'06), Sep. 2006.
"Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors," X. Shi, Z. Yang, J-K. Peir, L. Peng, Y. Chen, V. Lee, and B. Liang, 20th IEEE Int'l Parallel & Distributed Processing Symp. (IPDPS'06), April 2006.
"Signature Buffer: Bridging Performance Gap between Registers and Caches," L. Peng, J-K. Peir, and K. Lai, 10th Int'l Symp. on High Performance Computer Architecture (HPCA'04), Feb. 2004, pp. 164-175.
"Address-Free Memory Access Based on Program Syntax Correlation of Loads and Stores," L. Peng, J-K. Peir, Q. Ma, and K. Lai, IEEE Transactions on VLSI Systems, Vol. 11(3), June 2003, pp. 314-324.
"Bloom Filtering Cache Miss for Accurate Data Speculation and Prefetching," J-K. Peir, S. Lai, S. LU, J. Stark, and K. Lai, 2002 Int'l Conf. on Supercomputing (ICS'02), June 2002, pp. 189-198.
"Direct Load: Dependence-Linked Dataflow Resolution of Load Address and Cache Coordinate," B. Chung, J. Zhang, J-K. Peir, S. Lai, K. Lai, 34th Int'l Symp. on Microarchitecture (MICRO'01), Dec. 2001, pp. 76-87.
"Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores," Q. Ma, J-K. Peir, L. Peng, and K. Lai, 2001 Int'l Conf. on Computer Design (ICCD'01), Sep. 2001, pp. 54-61.
"Functional Implementation Techniques for CPU Cache Memories," J-K. Peir, W. Hsu, and A. Smith, IEEE Transactions on Computers, Special Issue on Cache Memory and Related Problems, Vol. 48(2), Feb. 1999, pp. 100-110.
"Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology," J-K. Peir, Y. Lee, and W. Hsu, 8th Int'l Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS'98), Oct. 1998, pp. 240-250.

CAREER Award, National Science Fundation, 1996
IBM Faculty Research Development Partnership Award, 1995
Two Best Paper Awards, IEEE Int'l Conf. on Computer Design, 1990, 2001
IBM Invention Achievement Award, 1992
Associate Editors IEEE Trans. on Parallel and Distributed Systems, and Journal of Parallel and Distributed Computing