##-------------------------------------------------------------
## AIM Project - University of Florida
##-------------------------------------------------------------
## SIMD Model of Computation -- ASC-to-ASM and ASM-to-BVC translation table
##
## Revisions:  M.S. Schmalz   08 Jun 2000  Added documentation
##
##-------------------------------------------------------------
## ASC -> ASM Translation Table
##-------------------------------------------------------------

SNEGX -> 1,100,SCA-NEG-FIXED        #Format: <N_ASMcodes>,<transln-time>,<type>
	IINEG 2                     #        <ASM-opcode> <no-operands>
INEGX -> I\MESH,100,IMG-NEG-FIXED   #Note:   <N_ASM> = 'I' denotes image size
	{IINEG 2}*(I\MESH)          #        computed from ASC operand#1 parm's
TNEGX -> T\MESH ,100,TMP-NEG-FIXED   #Note:   <N_ASM> = 'T' denotes image size
	{IINEG 2}*(T\MESH)          #        computed from ASC operand#1 parm's
IABSX -> I\MESH,100,IMG-ABS-FIXED 
	{IIBFLP 2}*(I\MESH)
ISQRTX -> I\MESH,100,IMG-SQRT-FIXED 
	{IISQRT 2}*(I\MESH)
ISINX -> I\MESH,100,IMG-SIN-FIXED 
	{IISIN 2}*(I\MESH)
ICOSX -> I\MESH,100,IMG-COS-FIXED 
	{IICOS 2}*(I\MESH)
ITANX -> I\MESH,100,IMG-TAN-FIXED 
	{IITAN 2}*(I\MESH)
IISINX -> I\MESH,100,IMG-ISIN-FIXED 
	{IIISIN 2}*(I\MESH)
IICOSX -> I\MESH,100,IMG-ICOS-FIXED 
	{IIICOS 2}*(I\MESH)
IITANX -> I\MESH,100,IMG-ITAN-FIXED 
	{IIITAN 2}*(I\MESH)
IADDX -> I\MESH+3,200,IMG-ADD-FIXED 
	IILOD 1
	IILOD 1
	{IIADD 3}*(I\MESH)
	IISTO 1
ISUBX -> I\MESH,200,IMG-SUB-FIXED 
	{IISUB 3}*(I\MESH)
IMULX -> I\MESH,200,IMG-MUL-FIXED 
	{IIMUL 3}*(I\MESH)
IDIVX -> I\MESH,200,IMG-DIV-FIXED 
	{IIDIV 3}*(I\MESH)
ILOGX -> I\MESH,200,IMG-LOG-FIXED 
	{IILOG 3}*(I\MESH)
IEXPX -> I\MESH),200,IMG-EXP-FIXED 
	{IIEXP 3}*(I\MESH)
ICHIX -> I\MESH,200,IMG-CHI-FIXED 
	{IICMP 3}*(I\MESH)

## Generalized convolution: Ops are {MUL SHF {MUL ADD SHF}*(T-2) MUL ADD}
##                          so there are 2 + 3(T-2) + 2 = 3*(T-2)+4 ASMs per
##                          image pixel (hence the *I at the end of the loop)

ITGCNX -> I*(3*(T-2)+4),200,I-T-GCN-FIXED      
	{IIMUL 3,SHF 0,{IIMUL 3, IIADD 3, SHF 0}*(T-2), IIMUL 3,IIADD 3}*I

IIGCNX -> I*(3*(I-2)+4),20000,IMG-GCN-FIXED
	{IIMUL 3,SHF 0,{IIMUL 3, IIADD 3, SHF 0}*(I-2), IIMUL 3,IIADD 3}*I

ISUMX -> I-1,200,IMG-SUM-FIXED 
	{IIADD 3}*(I-1)

ILUTX -> I,200,IMG-LUT-FIXED 
	{IILOD 1}*I

IOUTX -> I,200,IMG-OUT-FIXED 
	{IISTO 1}*I

##--------------------------------------------------
## ASM -> BVC Translation table for SIMD MOC
## Note: Assume BVC takes one cycle of mesh clock
##--------------------------------------------------
 
IINEG -> 1,10,SIMD-BITFLIP-16      #Format: <N_BVCs>,<xlatn_time>,<type>
	SIMD-BITFLIP-16 2          #          <BVC_opcode> <N_operands>
IIBFLP -> 1,10,SIMD-BITFLIP-16 
	SIMD-BITFLIP-16 2
IISQRT -> 1,10,SIMD-LUT-SQRT 
	SIMD-LUT-SQRT 2
IISIN -> 1,10,SIMD-LUT-SIN
	SIMD-LUT-SIN 2
IICOS -> 1,10,SIMD-LUT-COS
	SIMD-LUT-COS 2
IITAN -> 1,10,SIMD-LUT-TAN
	SIMD-LUT-TAN 2
IIISIN -> 1,10,SIMD-LUT-ISIN
	SIMD-LUT-ISIN 2
IIICOS -> 1,10,SIMD-LUT-ICOS
	SIMD-LUT-ICOS 2
IIITAN -> 1,10,SIMD-LUT-ITAN
	SIMD-LUT-ITAN 2
IIADD -> 1,10,SIMD-ADD-16
	SIMD-ADD-16 3
IISUB -> 1,10,SIMD-SUB-16
	SIMD-SUB-16 3
IIMUL -> 1,10,SIMD-MUL-16
	SIMD-MUL-16 3
IIDIV -> 1,10,SIMD-DIV-16
	SIMD-DIV-16 3
IILOG -> 1,10,SIMD-LUT-LOG
	SIMD-LUT-LOG 3
IIEXP -> 1,10,SIMD-LUT-EXP
	SIMD-LUT-EXP 3
IICMP -> 2,20,SIMD-CMP-16
	SIMD-SUB-16 3
	SIMD-CMP-16 3
IILOD -> 1,20,SIMD-LOD-16
	SIMD-LOD-16 1
IISTO -> 1,30,SIMD-STO-16
	SIMD-STO-16 1
SHF -> 1,2,SIMD-SHF-16
	SIMD-NSHF-16 0