The existing PIM scheduler employs a heuristic optimizer to produce a sequence of PIM server calls that conform to a predetermined, fixed protocol. We plan to expand the PIM protocol to yield AIM server calls that would (a) admit a wider range of datatypes or image/signal representations and (b) support interactive debugging. We plan to drastically enhance the PIM scheduler by adding the following modules:
High-level (Symbolic) Debugger would perform consistency checking, dependency analysis, and rewriting (as required) on a given expression tree to reduce erroneous or costly dependencies and subtree redundancy. Optimizing the subtree segmentation problem for various type, size, and form of subtrees typically encountered in ISP/ATR algorithms would be a key research topic.
Status Manager (SM) would gather status information of hardware/software modules and hardware interconnects via planned add-ons to existing libraries. The SM would post status information to a data structure (similar in concept to a blackboard), that would be queried by the AIM debuggers (modules A and C of this list). A key technical issue is the development of a unifying protocol for status reporting that would simplify the augmentation of hardware libraries to include a status interface partition.
Low-level (Execution) Debugger would accept status information from the Status Man ager and refine Scheduler output to produce near-optimal sequences of AIM server calls, to account for:
(1) Hardware reconfigurability as well as software reconfiguration strategies such as out-of-order execution and heuristic selection of alternative processing methods (e.g., multi-SIMD mesh reconfiguration via microcode swapping), to nearly optimize the time-space bandwidth product for a given configuration;
(2) Functionality and accuracy of available hardware, for example: (a) supported operations and associated computational precision, (b) hardware interconnect status at multiple resolution levels (e.g., network, subnet, processor, PE, chip, or gate); and (c) hardware faulting or failing behaviors (monitored at an effective resolution level, i.e., where monitoring overhead does not significantly impact algorithm performance).
The AIM Hardware Layer would contain equipment and associated hardware interface libraries (each specific to a given machine type) that would have (a) control/reconfiguration partitions and (b) a partition that would interface with hardware to report machine status. The status partition would derive from existing test routines (written in microcode) provided by hardware manufactur ers or subcontractors, who would provide technical assistance for library development. Subcontractor interactions would directly support development of these capabilities.
Unifying model of computation (MOC), partitioned into three levels: network, processor, and gate. Each level would have a specific set of attributes for status monitoring and performance characterization, from which instances of various devices are derived (e.g., processing elements and chips are derived from the Processor Level). The MOC would be graph-structured to facilitate algorithm-to-architecture mapping using transformations between the algorithm dataflow graph and that of target architectures.
Requirements and design for debugging for reconfigurable architectures using (a) a source-code to middleware translator to detect syntax errors, (b) a symbolic debugger to detect and correct dependen cies, extract repeated subtrees, etc., and (c) and execution debugger to detect and generate alternative mapping or scheduling strategies for faulting or failing hardware components.
(A) Due to its architecture independence, the AIM software could be configured to function with a variety of parallel and networked computers, thus realizing portability of AIM to various military, government, medical, and business applications, as discussed previously.
(B) The Lockheed-Martin PAL processor, together with AIM, would permit high-bandwidth image and signal processing (2.5 GFLOPs per PAL-II board) using interfaces such as Khoros (currently supported). This would realize robust, near-optimal, high-bandwidth SIMD-parallel computing for a variety of military and medical applications, at a reason able cost (less than $4k per board projected for PAL-II).
(C) Advanced reconfigurable computers based on field-programmable gate arrays (FPGAs) would be more feasible in practice, since AIM would provide a means for integrating such processors. Examples of such machines are Virtual Machine Works emulator boards, and various reconfigurable signal processors developed by Lockheed-Martin Sanders using Xilinx XC3000 and XC4000 PCI-compatible FPGA development platforms.
As discussed in specific technology transitions 1-3, below, results of the proposed study would immediately benefit military applications that required dynamic reconfigurability, especially as low-level tools for reconfiguring such processors are further developed and fielded.
Given the long history of success at UF in product development and technology transfer (summarized below), enhancement of product quality, scope, and delivery could feasibly be achieved in collaboration with the sponsor, subcontractors, and affiliated organizations. This would further support DoD goals of increasing research and development capabilities of military, government, university, and industrial organizations.
For example, the following specific technology transitions are a feature of our research during academic year 1997-98:
1. Lockheed-Martin Electronics and Missiles, Inc., Orlando FL -- will receive direct technology transfer as a result of our subcontract with this organization. Knowledge to be transferred will include, but not be limited to (a) new design concepts for the PAL SIMD processor, with performance and reliability analyses derived from our simulations using the AIM SIMD model, (b) improved fault isolation and remediation procedures for SIMD-parallel processors, (c) results of mapping various image processing and ATR algorithms to PAL, and (d) improvements in the PIM control software for PAL that are suggested by our AIM research.
2. Lockheed-Martin Sanders, Inc., Nashua NH -- will receive direct technology transfer as a result of our subcontract with this organization. Knowledge to be transferred will include, but not be limited to (a) new design concepts for reconfigurable computing using FPGAs, with performance and reliability analyses derived from our simulations using the AIM FPGA model, (b) improved fault isolation and remediation procedures for various types of FPGAs, (c) results of mapping various image processing and ATR algorithms to FPGA simulators and hardware, and (d) an assessment of advanced technology requirements for future FPGA implementations.
3. USAF Wright Laboratory (WL), Eglin AFB, FL -- UF has a long, productive relationship with WL/MN and plans to directly transfer knowledge to various POCs managing applications in advanced ATR, guidance, targeting, and fire control systems, etc. This will be done through an existing USAF contract with WL/MN.
Planned future technology transition paths that have not yet been implemented include contacting FPGA manufacturers (e.g., Xilinx) and FPGA-based computer manufacturers (e.g., Virtual Machine Works). Our initial conversations with such organizations indicated that they could benefit from our research results. In late Autumn 1997, we plan to ask if they are still interested in receiving research reports, papers, etc. that describe our research in FPGA fault isolation, which was their primary interest. This technology transfer could potentially faciliate improved reliability of FPGAs as well as FPGA-based computing devices.