Proposal Abstract
For the Further Development of a Proposed
Cost-Effective Adiabatic Digital System Technology
for Low-Power Computing Applications

Dr. Michael P. Frank

University of Florida, CISE Dept.

Introduction

Due to recent research advances by our group, together with the progress of some enabling technologies, we believe that adiabatic circuit techniques are now a low-power computing technology whose time has come. The field of adiabatics is now ready for a more intensive, aggressive R&D investment, for the purposes of pursuing both a variety of present-day low-power applications, and also for dealing preemptively with some of the fundamental physical limits to computation that lie not far ahead.

We invite the initiation of a serious pattern of research investment in this program from industry, to enable us to implement the sophisticated combination of advanced adiabatic techniques that we have been developing, and to build several demonstration chips illustrating the ultra-low-power capabilities of this technology.

This document outlines some of the elements of the research, but is not a full proposal with detailed technical content. Organizations who are interested in possibly funding this research are asked to request a more detailed proposal.

The Proposer

The leader of this project, Dr. Frank, studied VLSI design, adiabatic circuits, reversible computing, and the physical limits of computation at MIT under Dr. Thomas F. Knight for his Ph.D. In the course of his work, Dr. Frank designed and fabricated the first fully-adiabatic universal processor chip, invented reversible architectures and programming languages, and gave the first theoretical demonstration that reversible computing is asymptotically better-performing than conventional computation under realistic physical models of computation. These groundbreaking results have been published in the journal Nanotechnology and in the conference proceedings Unconventional Models of Computation. Dr. Frank is currently working on a book Reversible Computing to be published by MIT Press, as well as several new journal articles.

Dr. Frank is presently a tenure-track faculty member at the University of Florida’s Computer & Information Science & Engineering Department, and is continuing his research and attempting to obtain funding to operate a substantial adiabatic circuits research & technology development program at UF, via a number of proposals written in collaboration with several colleagues in the Electrical and Computer Engineering Department at UF, and with colleagues in the area of silicon nanoelectronics at Clemson university. So far, Dr. Frank’s research has evoked marked interest from personnel at companies including IBM, Texas Instruments, Intel, Harris, Intersil, Sandia, Siemens, and Nortel Networks, as well as from the press. It seems that it is only a matter of (a hopefully short) time before one of these companies decides to take a leadership role in this field, and follow through on their expressed interest by offering an actual research grant or contract.

Elements of the technology we propose include:

Automatic conversion of existing general-purpose or application-specific logic designs (no new logic design work is required to demonstrate the technology)
Leveraging of existing industry-standard MOSFET fabrication technology (no new device structures required).
A sophisticated refinement we have developed of the “split-level” adiabatic technique first described by Younis and Knight at MIT for implementing adiabatic logic in CMOS.
A simple, automatic circuit-level transformation we have invented for transforming arbitrary conventional, irreversible logic networks into adiabatic, reversible ones that approach perfect logic-level reversibility, as closely as is required for any achievable level of power savings, with relatively low cost-performance overhead.
A particularly simple circuit-level implementation that we have discovered of an algorithm invented by Charles Bennett of IBM Research in 1989 that can be used to further minimize the cost-performance overhead of reversible computations.
An optimization of the parameters of Bennett’s algorithm to minimize cost-per-performance for any given level of power-per-performance reduction, using an analytic solution we have derived.
Fourier networks of shape-tailored MEMS resonators, as a solution we have devised for providing relatively low-f but high-Q resonant voltage waveforms of the right shape for delivering and recovering energy to/from the adiabatic circuits in question with very small losses.
Use of high-k dielectrics as needed to prevent gate-to-channel tunneling from becoming a dominant source of power dissipation when operating in the ultra-low-power regime.
Multiple layers of active circuits, to prevent the conventional-to-adiabatic circuit transformation from increasing circuit area requirements and interconnect wire lengths significantly in our reversible circuits, compared to conventional ones. Note that cooling these multi-layer circuits is not a problem, since they dissipate less power per unit area than conventional single-layer circuits!
Use of scalable parallel architectures and algorithms to compensate for lower circuit frequencies by increasing the degree of parallelization of the processing resources, to meet the overall throughput demands of a particular application.
An analytical methodology and software tools that comprehensively encompass the inter-relationships between the above technology elements, to produce a realistic system-design-time estimate for the actual cost of a system implementation, as a function of the product’s power and performance requirements.

The only fundamental limit to the power-performance efficiency of adiabatic technology that is not specifically addressed by the above suite of technologies is the decreasing Ion/Ioff ratio exhibited by MOSFETs as scaled threshold voltages approach small multiples of the room-temperature thermal voltage of 26 mV. However, based on our analysis of the Ion/Ioff ratios specified by the ITRS semiconductor roadmap, this ratio will not become a significant limiting factor on the maximum power savings achievable via adiabatics until about the year 2008.

Beyond this time, adiabatic low power computing will require new device structures that present higher energy barriers to leakage, despite their nano-scale sizes. (But very soon afterwards, even non-adiabatic low power technologies will require this also.) There is nothing fundamentally impossible about low leakage in nanodevices; e.g., Eric Drexler’s proposed rod logic structures have an extremely long thermal half-life for bit-energy storage, despite their molecular size, because the energy barrier presented by the overlapping of rods’ electron orbitals is so great. Similarly, successful (non-leaky) nanoelectronic devices will likely need some method of isolation between circuit nodes that is more effective than the field-effect-induced potential barrier that is used to turn off MOSFETs; thus the requirement for a different structure at that time. But, we re-emphasize that for the near term, no new device structures are required to implement adiabatic technology.

Needs:

For near-term technology generations, all the elements of the proposed technology are straightforward to develop; they rely only on existing, well-understood underlying technologies and processes. It is merely a matter of putting the pieces together with an eye towards the overall requirements of the ultra-low-power regime. As researchers, we know how to do it. All that is needed are design personnel, design tools, and fabrication facilities (in other words, funding) to do the grunt work to put together a complete demonstration adiabatic system that achieves a significant power-per-performance reduction, compared with a conventional irreversible design.

There is also a marketing need, which is to locate a present-day application domain (or perhaps invent an entirely new application) where power cost rather than logic hardware cost is the dominant limiting factor on meeting the application’s requirements, to such a large extent so as to justify the increase in logic hardware cost/performance required to meet the application’s power/performance requirements adiabatically. (The cost increase factor scales as roughly the square of the power reduction factor – down to linearly for some special-purpose computations.)

Thirty-five years from now, we expect that the marketing side of this will be easier, because most computing applications will be power-limited, since energy transferred per bit operation will have reached its fundamental limit near kT, whereas cost per bit-device may well continue declining, due to improvements in nano-manufacturing technologies. But, there may be some highly power-limited applications even today.

Potential Near-Term Applications:

Spacecraft – The high cost-per-weight of launching computing-related power supplies, solar panels, and cooling systems into orbit imposes a demand for adiabatic power reduction in spacecraft in which these components weigh a significant fraction of total spacecraft weight (and the computer itself does not).
Implanted medical devices – Such as automatic drug-delivery systems or pacemakers. These may need to do significant computation continuously to execute decision-making algorithms to determine whether to deliver a drug or electrical stimulation at a given moment based on sensor inputs. However, one obviously wishes to minimize their power requirements, since the patient will wish to be able to move around freely for long periods of time without replacing batteries or recharging the device. The device might even be powered by a chemical engine using the body’s own resources.
Laptop/handheld/wearable computers – Obviously, here there are other power dissipation sources such as displays, disks and transmitters to consider. But in any products where computation is the dominant component of total power (but not total weight), the application of adiabatics will be beneficial. Adiabatic techniques should even allow conversion to batteryless (fully solar or RF powered) operation in small wearables .
Wallet “smart cards” – An example of a wearable computer for personal & financial data, digital cash, etc.
“Smart tags” on inventory – Used for locating objects. Smart tags may sit on boxes in warehouses for months, listening to the airwaves and doing low-power signal processing. If they hear a location request that includes their own id number or a template matching their description, they locate themselves using GPS and broadcast a signal giving their coordinates. Obviously these devices need very low power in order that they can sit around for a long time and not go dead. With adiabatics, they could even be powered by ambient EM via their receiving antennas.

The Request:

We are seeking a semiconductor-industry sponsor, with access to advanced SOI and multi-layer chip technologies, who agrees with us that the near-term commercial prospects for adiabatic technology are significant, and that its long-term importance for the computing industry is enormous. Upon their request, we will write a more detailed proposal for this or any closely related development program to any interested sponsor. Upon approval, we request a significant initial investment (5 to 6 figures) to enable us to pursue the development of this technology with increased vigor in a university setting. Alternatively, offers of research positions with a budget that would allow us to pursue this work in-house in an industry setting would also be considered.