Lectures 10-14 homework

Lecture 10 homework

1. [1 point] Calculation.  Like lecture 8 exercise 1, but for each system you pick, calculate its maximum rate of transitions between distinguishable states, using the Margolus-Levitin bound, and assuming the ground state energy is 0.  What is the maximum rate if free energy, rather than total rest mass-energy, is used in the calculation?
2. [10 points] Research problem.  Study some other definitions of free energy (e.g. Gibbs free energy, Helmholtz free energy) from the thermodynamics, physical chemistry, or quantum statistical mechanics literature.  You will find that most standard definitions are not as general as ours, in that they usually refer to restricted classes of systems (e.g. chemical solutions) rather than to arbitrary systems.  Anyway, try to figure out:  Which, if any, of the standard definitions corresponds (in the systems for which it is defined) to the definition given in today's lecture?  Or, if none of them do, can you come up with an alternative definition of free energy that matches one of the standard definitions, and yet is phrased in gneral terms like our definition?

Lecture 11 homework

Lecture 12 homework

1. [7 points] Short research paper.  Write a short paper, backed up by reference sources, discussing the pros and cons of constant-field scaling.  Is it a good idea?  If not proportionally to length, how should voltages be scaled?
2. [10 points] Research problem.  Do some background research on the effects of low temperature on semiconductor electrical and performance characteristics.  Can lowering the temperature help to improve Ion/Ioff ratios as device size and voltage scales down?
3. [5 points] Analysis.  In class it was mentioned that there is a limit to how much changing the shapes (thickness and separation) of wires can reduce their RC delay, given that the wires have to fit within a limited space.  Construct a appropriate model that will let you prove this is the case.  Example: (You can modify this as you see fit.)  Suppose that n wires connect a small (radius r) roughly-spherical logic block to other endpoints which are uniformly spaced on the surface of an enclosing sphere at a (larger) distance R around the logic block.  Assume the wires are also uniformly spaced apart from each other, to minimize their pairwise capacitance.  By symmetry, assume that each wire is circular in cross-section and that they all have the same thickness profile t(x) ranging over radial distances x between r and R.  From t(x) you can derive the resistance along and approximate mutual capacitance between neighboring wires as a function of x.  Remember to take the changing wire separation into account.  Respecting the constraint that wires must not overlap (which would give you a negative capacitance), find the optimal t(x) profile using, e.g., a perturbative functional analysis, knowing that any small t'(x) function added to the optimal t(x) must increase the total RC delay.   Give an expression for this RC delay as a function of r and R.  If both r and R are scaled down uniformly, while n remains the same, how does the RC of the optimal configuration scale?
4. [1 point each, max 5 pts] Analytical Exercise.  Can you find any errors in the slides (any relations that are not correct as a first-order approximation)?  Also, can you suggest any additions to the slides, i.e., other electrical or performance characteristics not mentioned, for which you can find a simple first-order scaling relation?
5. [10 pts] Quantitative Analysis.  The lecture pointed out that the number of devices accessible by scaled wires within a constant number of gate delays decreases as all dimensions are scaled (the detailed slide on this was not shown in class till lecture 13).  Try to make this point quantitative.  Use data from the 2001 ITRS roadmap specifying transistor CV/I delays, gate density, wire characteristics, etc., to calculate the maximum number of logic gates within the reach of a minimum-width wire of a length such that its RC delay is a constant number (say 10) times the transistor CV/I delay.  Plot your results as a function of year.  Bonus 5 points: If you did exercise 3 above, combine it with this exercise to show how the number of gates reachable within 10 CV/I delays scales scales as a function of year, if arbitrary wire configurations (as opposed to just minimum-width wires) can be used.   Assume there are 100 wires coming out of the logic block under consideration.

Lecture 13 homework

1. [7 points] Short research paper.  In lecture the idea was mentioned of using diamond as an insulator for SOI structures due to its high thermal conductivity (the highest known).  Do some background research and try to figure out whether this could work.  Are there problems due to the band structure of diamond (e.g., will charge carriers from the Silicon be injected into it)?  What are the difficulties that would or could be faced in integrating chemical-vapor-deposited diamond into the semiconductor fabrication process?
2. [7 points] Short research paper.  High-k (dielectric constant) materials are needed to keep gate capacitance-per area growing without thinning the gate dielectric to the point where leakage due to quantum tunneling is a problem.  Do some research to determine what materials are currently being investigated for this purpose.  Summarize what you discover.

Lecture 14 homework

1. [5 points] Analysis.  Can you tighten the lower bound given in lecture on the CV² energy per logic node in order for N operations to be performed reliably?  Hint:  The ensemble of states described in lecture included only states where exactly 1 of the bits was high.  What if you also include states having 0 high bits?  2 high bits?  What is the tightest bound you can derive by this entropy-based method, as a function of N?  Give a table showing the minimum CV² per bit, for Ns that are various powers of 2 (starting from N=1).
2. [5 points] Analysis.  Use data from the 2001 ITRS roadmap to update the calculations of minimum entropy generation per switching event shown in the green book, sec. 7.1.3, pp. 156-162.  Give your results in a similar table to the ones there.  When listing minimum gate capacitance, state the values in terms of the room-temperature thermal capacitance.
3. [2 pts] Analysis. Assume we have a cooling system capable of handling a peak heat flux of 10 W/cm².  Assuming the machine's internal operating temperature is 350 K (and it contains no heat engine), combine this with the figures for minimum entropy generation per bit-op from table 7.2, p. 158 of the green book to calculate the maximum rate of bit-operations per unit of outer-surface area in computers built with each year's technology.  Express your results in bit-ops per nanosecond per square micron.  (By what factor would these rates improve if the machine could run an ideal heat engine internally and emit heat at room temperature (300 K)?)  For each year's technology, what is the maximum rate of operation in a handheld-size machine with a surface area of 100 square centimeters?  (Note that at 1kW total dissipation it might be uncomfortable to hold this machine in your hand - think about holding a space heater.  Hopefully it is at least aiming the hot air or EM radiation away from your hands and face.)
4. [3 pts] Analysis. Extrapolate the entropy generation trends from table 7.2 further out into the future, assuming a constant rate of decrease of log(entropy generation per op).  Plot the maximum reliability factor N as a function of year.  What year would the reliability become, say, lower than 100 (i.e., more than 1 error per 100 ops)?