CIS 4930.1194X/6930.1078X Spr.'00
Lecture 17 (Feb. 18) Notes:
Adiabatic Circuits Wrap-Up

[The slides for this lecture are available on reserve, under "Slides for lecture 17."]

Today is just a fairly short "conclusion" sort of lecture, to make some final points and then sum up the last two weeks on adiabatic circuits.  The last part of class I want to reserve for questions/discussion.  I'll throw out candy to people who ask good questions.

Scaling Adiabatic Techniques to Future MOSFET Technology Generations

The question naturally arises as to how the performance and energy characteristics of adiabatic circuit techniques will scale as MOSFET technology continues to improve over the next 10 years or so.  (Slide.)

Recall that adiabatic dissipation per operation is E=CV^2 (RC/t), whereas irreversible circuits incur E=1/2 CV^2 dissipation.

Consider a shrink factor of s over some period of years, that is, all lengths L are shrunk to L/s.

As we saw in week 3 of the course, capacitance scales roughly as 1/s, an voltages too (at least in the short term, until leakage becomes a serious problem).

So CV^2 goes as s^-3.  This factor appears in both the adiabatic and non-adiabatic dissipation and so factors out of any comparison of the energy savings from adiabatic circuits.  The remaining factor is RC/t.

We also saw that wire resistance as s, and transistor resistance stays roughly constant.  Presently, transistor resistance still dominates in locally-connected circuits, so in the short term R~1 (total resistance roughly constant) and so RC~1/s.  (Total RC delays decrease).  This is exactly why clock speeds are continuing to get faster: t~1/s.

The factor RC/t giving the energy advantage of adiabatic circuits therefore is not changing, to first order, as technology improves, if t is a fixed multiple of RC delay.  (Fixed clock slowdown ratio for adiabatic circuits.)  However, another way of looking at it that the clock speeds for a given adiabatic energy advantage continue to increase.

However, for systems such as multi-layer circuits that are dissipation limited, we might not be able to run faster than a certain clock speed; or for some applications we might not need to.

At a fixed clock speed (fixed t), the dissipation of adiabatic circuits compared to ordinary circuits therefore scales as 1/s as circuits shrink.

What if we are in a scenario where we have a constraint of a certain total system size (volume) and a certain power consumption?  How does the maximum rate of raw computation (ops/sec) compare in adiabatic and non-adiabatic approaches?

The next slide shows the algebra needed to see that the ratio between adiabatic and conventional performance goes as square root of (s/P), where s is the shrink factor and P is the power limit.

So with the power constraint constant, as devices shrink the adiabatic approach becomes capable of increasing raw performance compared to the conventional approach, by a factor of sqrt(s).

However, if you can improve the total power throughput (both power delivery & cooling) by some factor, then this decreases the adiabatic advantage by the square root of that factor.

Note also that all this is for the near term only, before wire resistance starts to dominate.  Once it does, RC will stop decreasing, clock speeds will stop improving, and the adiabatic advantage for given total system volume & power will stop improving.

Another factor limiting the adiabatic advantage is that as voltages approach thermal voltages, leakage currents increase exponentially, limiting the potential advantages of adiabatic operation.  So actually the advantages may decrease as technology develops.

The flip side of this coin is that if you remove the size constraint, and you care only about total energy efficiency per op for a non-demanding low-performance application (e.g. a digital watch with a battery that never runs out), then if you simply refuse to scale down the circuits, and instead scale them up, you can in principle continue lowering the dissipation almost as much as you want because leakage will become increasingly insignificant once you can raise voltages again.  But that's not a practical approach except in applications that care only about energy extremely rabidly.

Another way out is that you can continue to scale down voltages without leakage if you lower the temperature, but this has other affects as well, such as decreasing the charge carrier concentration in the semiconductors, which effectively reduces conductance.  You can alleviate this to some extent by increasing the dopant concentration, but there are limits to that as well.

Besides which, if one is going to low temperatures, one might want to look at alternative superconducting devices, which have essentially zero resistance and offer a lot of promise for amazingly low-energy logic.  We'll talk about that technology next week.

Also, even aside from superconductors, at very small sizes a number of other quantum effects come into play which one might harness to create devices that operate on fundamentally different physical principles than do MOSFETs, as we saw in week 4.

Wrap-Up

In conclusion, here are the main take-home messages of the last 2 weeks:

- "Adiabatic charging" can in principle reduce the energy dissipation of digital switching operations to levels less than kT ln(2), that is, generating less than 1 bit of physical entropy, although in practice in real circuits this may or may not be achievable, depending on the current leakage properties of a given technology.  (It's definitely possible in technologies tailored for low leakage.)

- General purpose, universal, pipelined sequential logic can operate *solely* via adiabatic charging.  However, it has to be reversible at the logic level to do so.

- One can straightforwardly build universal reversible computers, although some programming and algorithmic issues are a bit different than in normal machines (issues to be discussed later).

- So far, really good adiabatic power supplies seem hard to find.  There are a number of fairly good techniques out there, but it's not yet clear how to design a fully electrical supply (with no moving parts) that has high Q*f, flat-topped waveforms, AND all the right scaling properties.

- Unfortunately, the limit of scaling for MOSFET technology doesn't appear to favor adiabatic operation, due to increasing leakage currents as voltage barriers shrink.

- Conclusion: Partial reversibility may be useful in the short term (next few years) for energy-limited applications, but in the medium term (near the limits of MOSFET technology, 10-20 years from now) it becomes less useful, but in the longer term, when we switch to a more quantum-effected technology such as quantum dots or superconductors, resistance*leakage may decrease again, and then it adiabatic approaches may become useful again.

- In the very long term (starting perhaps 30-50 years from now, and beyond), we can foresee a high demand for good reversible techniques, as they offer the only possible way to exceed the computing-rate limits that would otherwise be set by the available power and cooling technology due to the Landauer principle (erased bits become entropy).