Heon-Mo Koo

Office: E401, CSE Building

E-mail: hkoo AT cise.ufl.edu

Address: P.O. Box 116120 Gainesville, FL 32611 USA

About me

I am a Ph.D. candidate at the Department of Computer and Information Science and Engineering (CISE) at University of Florida and working with Prof. Prabhat Mishra.

Research Interests

• Formal Verification
• Test Generation for Validation of Microprocessors
• Confluence of Functional Verification and Manufacturing Test Generation
• Functional Modeling and Validation of Multimedia Systems

Publications

1. Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra and Magdy Abadir, Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study, IEEE International Workshop on Microprocessor Test and Verification (MTV), pages -, Austin, Texas, USA, December 4-5, 2006.
2. Heon-Mo Koo, Prabhat Mishra, Functional Coverage-driven Test Generation for Microprocessor Verification, Korean-American Scientists and Engineering Association US-Korea Conference (UKC), Teaneck, New Jersey, USA, August 10-13, 2006.
3. Heon-Mo Koo, Prabhat Mishra, Test Generation using SAT-based Bounded Model Checking for Validation of Pipelined Processor, ACM Great Lakes Symposium on VLSI (GLSVLSI), pages 362-365, Philadelphia, Pennsylvania, USA, April 30 - May 2, 2006.
4. Heon-Mo Koo, Prabhat Mishra, Functional Test Generation using Property Decompositions for Validation of Pipelined Processors, ACM/IEEE Design Automation and Test in Europe (DATE), pages -, Munich, Germany, March 6-10, 2006.
5. Prabhat Mishra, Heon-Mo Koo, and Zhuo Huang, Language-driven Validation of Pipelined Processors using Satisfiability Solvers, IEEE International Workshop on Microprocessor Test and Verification (MTV), Austin, Texas, USA, November 3-4, 2005.
6. H. Kim, K-S. Kim, S-G. Jeong, Heon-Mo Koo and I-C. Park, A Single-chip MP @ HL HDTV Decoder with Integrated Audio Decoding and Display Processing Units, International Conference on Consumer Electronics (ICCE), USA, 2000.

Technical Reports

1. Heon-Mo Koo and Prabhat Mishra, Functional Test Generation using SAT-based Bounded Model Checking, CISE Technical Report # 05-008, University of Florida, 2005.

TA

• CDA 5155: Computer Architecture Principle - Spring, 2005
• CIS 6930: Introduction to Embedded Systems - Fall, 2004
• CEN 4500: Computer Networking Fundamentals - Spring, 2004
• CEN5540: Computer and Network Security - Fall, 2003

Services

• Reviewer:
• Design Automation and Test in Europe (DATE)
• IEEE International Symposium on Circuits and Systems (ISCAS)
• Design Automation Conference (DAC)

Upcoming Conferences

Related Journals