 | Project Information |
Author & Title
Laurentiu Iancu
"3D Behavioral Model of Intel(R) ItaniumTM and Its Core
Pipeline"
Machine Architecture (project number 2.2) in the context of Aesthetic Computing.
The object to model is an Intel(R) ItaniumTM 64-bit microprocessor, its
core pipeline, and their behavior. The emphasis is on the 10-stage core pipeline, which is
modeled both with a Petri network and in a metaphorical representation. The 3D block diagram
of the Itanium is made with all three levels of cache memory.
Itanium represents the next generation of microprocessors for workstations and commercial
servers. It features a novel 64-bit Instruction Set Architecture (ISA), namely the
Intel Architecture IA-64. It also incorporates a 32-bit module to provide for
backward compatibility with the existent 32-bit programs.
The roadmap. Image from
Understanding the IA-64 Architecture
The IA-64 architecture is extremely intricate and not readily assimilable by developers.
Proof is that Intel's Developer Web Site provides
an extensive range of introductory materials to alleviate a developer's acquaintance with
IA-64 and the Itanium processor family.
This observation leads to a couple of conclusions, which motivated me to choose this
topic for my project:
- a dynamic, interactive 3D model can be very important and helpful in learning the
new concepts
- designing such a model is a difficult task and choices must be made with care
- an aesthetic representation of the behavior can make the exploration of the system
more enjoyable
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Project Description |
Overview
The Itanium processor alone is already too complex to model in detail. Its main
micro-architecture components are illustrated in the following picture.
The design. Image from
Intel(R) ItaniumTM Processor Microarchitecture Overview
Furthermore, the processor is best presented in the context of a typical computer system,
which would add even more complexity to the project. Therefore, my goal was to build a
basic model of the Itanium microprocessor with its central behavioral feature, the
core pipeline. The model illustrates the main components of the processor from a logical
standpoint, the dynamics of instruction execution, and the behavior of the core pipeline.
The constructed 3D world incorporates three main elements:
- an animated block diagram of the Itanium microprocessor, showing the dynamics of a
typical instruction execution
- a Petri network that models the 10-stage core pipeline
- an animated metaphorical counterpart of the Petri network, with which the user can
interact
In addition to exploring the whole world, each of the aforementioned elements can be surfaced
individually. Links are provided in the next sections of this document. A glimpse of the 3D
world is shown in the following snapshot. To explore the world, click on the image, or click
here. The VRML files that compose the project are:
project.wrl,
itaniumprotos.wrl,
itanium.wrl,
petrinetprotos.wrl,
petrinet.wrl,
metaphorprotos.wrl, and
metaphor.wrl.
The constructed 3D world
Instructions for exploring the 3D world
- click on the links above to open the world in this frame
- if necessary, click on the viewpoint to view the scene
- the block diagram will display a sequence of micro-operations, by highlighting the
active blocks
- in the center of the block diagram, two small components can be seen: the Petri
network and the metaphor
- click anywhere on the microprocessor to enlarge the Petri net and the metaphor; they
will come out with sound
- click on the metaphor (which is described below) to trigger one step of the
instruction execution
- when finished, click on the Petri network to place it and the metaphor back into the
microprocessor; they will go in with a sound
- you can walk or explore the world at any time; if you wish to examine only one of the
three elements, please refer to the sections below
The block diagram of the Itanium micro-architecture is shown in the image below. A snapshot
of the 3D counterpart follows. To examine the 3D block diagram, click on the snapshot, or
click here. Please note that you need to walk or zoom out in order to see the 3D
model. This is due to the fact that the VRML files of the three main components of the
project (block diagram, Petri net, metaphor) are inlined by the main file, project.wrl, which
applies translations appropriately. The links in these sections provide direct access to
those files. The VRML files that compose the microprocessor block diagram are
itaniumprotos.wrl and itanium.wrl.
The block diagram. Image from
Intel(R) ItaniumTM Processor Microarchitecture Overview
The 3D block diagram. Please zoom out when loading the VRML file
At the core of the micro-architecture there is a 10-stage pipeline. Thus, a maximum
of ten instructions can execute simultaneously, each instruction being in its own pipeline
stage at a given moment in time. Multiple functional units help reduce the contention between
instructions in stages where the micro-operations to execute require more than one clock
cycle to complete. The pipeline is depicted in the image below.
The core pipeline. Image from
Intel(R) ItaniumTM Processor Microarchitecture Overview
The intrinsic parallelism of the pipeline makes a Petri network suitable for
modeling its behavior. Each pipeline stage (where an instruction is processed) corresponds to a
transition of the Petri net. Each transition from one stage to the next (where an
instruction waits for its turn to enter the next processing stage) corresponds to a place
of the Petri net. Additional Petri net places are needed to model the synchronization. The
following figure depicts a 3D representation of the Petri network, and a piece of the 2D
counterpart. The basic geometry of the 3D representation of the Petri network can be viewed
here (files
petrinetprotos.wrl and
petrinet.wrl). This is not the metaphor.
A Petri network that models the behavior of the pipeline
A Petri network is a dynamic model itself. A metaphor needs to map both the places and
transitions, with the arcs that connect them, as well as the tokens, to corresponding objects of
a 3D world that the user would enjoy to explore. A good metaphor for a Petri network should
coherently represent all of its components. In general, the number of tokens may vary through
transitions when the model is run, which makes the choice of a creative metaphor more difficult.
However, in the modeled microprocessor pipeline, only one instruction can be in a stage at a
time.
A customized baggage inspection pipeline metaphor can fulfil these requirements.
The mapping is as follows:
- round platforms where baggage can be placed correspond to places of the
Petri net
- various detectors (such as metal detectors) that baggage is passed through
correspond to transitions of the Petri net
- conveyors that move the baggage correspond to arcs from places to
transitions and from transitions to places of the Petri net
- suitcases and grips correspond to tokens of the Petri net; suitcases
represent instructions being processed in the actual processor pipeline stages,
while grips (claws) show when a pipeline stage is available to receive a new
instruction
A claw will reach a piece of baggage and grip it to represent the merger of two tokens into one
through a transition. Conversely, a claw releases a suitcase and resumes its waiting position to
denote the split of a token into two. A claw alone will be viewed as one token and will mark an
available processor pipeline stage. A piece of baggage gripped by a claw will also be viewed as
a single token but will mark a busy processor pipeline stage.
The basic geometry of the metaphorical 3D representation of the Petri network can be viewed
here (files
metaphorprotos.wrl and
metaphor.wrl).
The baggage inspection pipeline metaphor
Several other ideas of metaphors that I previously considered are enumerated below. They are
more amenable to mapping finite state automata (rather than Petri networks) to 3D worlds. The
last two metaphors need an additional constraint for directed transitions.
- a city metaphor, with buildings corresponding to states and one-way roads
corresponding to directed transitions
- a mall metaphor, with stores corresponding to states and one-way escalators
corresponding to directed transitions
- a subway system metaphor, with stations corresponding to states and railway
tunnels corresponding to transitions
- a coal mine metaphor, with larger rooms corresponding to states and tunnels to
transitions
- a restaurant metaphor, with tables corresponding to states and carpets laid
between tables corresponding to transitions
- a tree metaphor, with fruits corresponding to states and lianas to
transitions
The objectives that I had set when approaching this project included the illustration of:
- the main components of the processor's micro-architecture
- the interconnections with the three levels of memory cache blocks
- a metaphoric representation of a Petri network that models the behavior of the
processor's 10-stage core pipeline
In constructing my 3D model, I followed these guidelines:
- be accurate conceptually, at the chosen level of abstraction
- be animated, as any computer continues to function as long as plugged in
- allow user interaction and be aesthetic
In attaining the last goal mentioned above, I had to address issues as:
- intuitive behavior, that can convey the concepts represented in the scene
- user frendliness
- enjoyable experience (animation and sound integration)
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Project Time Line |
Gantt Chart
The project due dates were the following:
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... Oct. 11 |
Oct. 12 ... Oct. 23 |
Oct. 24 ... Nov. 5 |
Nov. 6 ... Nov. 22 |
Nov. 23 ... Dec. 13 |
| Initial description |
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| Detailed description |
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| Example VRML world |
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Cancelled |
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| First demonstration |
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| Completed project |
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Extension granted |
I worked alone.